1. Field of the Invention
The present invention generally relates to comparator circuits and more particularly to comparator circuits exhibiting a relatively high-speed operation, while maintaining relatively low power consumption.
2. Description of Related Art
Persons of ordinary skill in the art understand terms and basic concepts related to microelectronics that are used in this disclosure, such as PMOS (p-channel metal-oxide semiconductor) transistor, NMOS (n-channel metal-oxide semiconductor) transistor, “gate,” “source,” “drain,” “voltage,” “current,” “circuit,” “circuit node,” “power supply,” “ground,” “rail-to-rail,” “clock,” “comparator,” “inverter,” “pull-up,” “pull-down” and “latch”. Terms and basic concepts like these are apparent from prior art documents, e.g. text books such as “Design of Analog CMOS Integrated Circuits” by Behzad Razavi, McGraw-Hill (ISBN 0-07-118839-8), and thus will not be explained in detail here.
A clocked comparator is an apparatus for detecting a sign of a differential signal in accordance with a timing defined by a clock. A differential signal comprises a first end and a second end. A clocked comparator receives the differential signal and outputs a logical decision in accordance with a timing defined by a clock. In a phase of the clock, a level of the first end (of the differential signal) is compared with a level of the second end (of the differential signal), and the logical decision (which is a resolution as a result of the comparison) is made. The logical decision is set to “high” (“low”) if the level of the first end is higher (lower) than the level of the second end. Merits of a clocked comparator are usually assessed by two factors: speed and power consumption. Speed of a clocked comparator refers to how fast it can resolve a small differential signal, where a level of the first end is very close to a level of the second end. Power consumption of a clocked comparator refers to the energy it takes to fulfill the comparison function. In reality, there is a trade-off between the speed and the power consumption. As known in prior art, it takes a longer time to resolve a comparison for a small differential signal than for a large differential signal. Therefore, to achieve high speed, a pre-amplifier is usually used, so as to amplify the differential signal and thus facilitate the task of resolving the comparison. The use of a pre-amplifier, however, increases the overall power consumption.